/*
检测起始位，即检测到数据输入引脚由高电平变为低电平，输出一个高电平脉冲

Rx_pin_in: 串行输入数据引脚
*/
module detect(clk,rst,Rx_pin_in,hl_sig);
input clk,rst,Rx_pin_in;
output hl_sig;
reg hl_f1;
reg hl_f2;

always @(posedge clk or negedge rst)
begin
	if(!rst)
	begin
		hl_f1<=1;
		hl_f2<=1;
	end
	else
	begin
		hl_f1<=Rx_pin_in;
		hl_f2<=hl_f1;
	end
end
assign hl_sig = hl_f2&~hl_f1;	
endmodule